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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4017B MSI 5-stage Johnson counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
5-stage Johnson counter
DESCRIPTION The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW to HIGH transition at CP0 while CP1 is LOW or a HIGH to LOW transition at CP1 while CP0 is HIGH (see also function table). When cascading counters, the O5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.
HEF4017B MSI
A HIGH on MR resets the counter to zero (Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the clock inputs (CP0, CP1). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
PINNING CP0 CP1 MR O0 to O9 O5-9 clock input (LOW to HIGH triggered) clock input (HIGH to LOW triggered) master reset input decoded outputs carry output (active LOW)
FAMILY DATA, IDD LIMITS category MSI Fig.2 Pinning diagram. See Family Specifications
HEF4017BP(N): HEF4017BD(F): HEF4017BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
January 1995
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5-stage Johnson counter HEF4017B MSI
Philips Semiconductors
Product specification
5-stage Johnson counter
FUNCTION TABLE MR H L L L L L L L X H L CP0 X H L X H CP1 X OPERATION O0 = O5-9 = H; O1 to O9 = L Counter advances 4. Counter advances No change No change No change No change 5. = positive-going transition = negative-going transition Notes
HEF4017B MSI
1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP0, CP1 O0 to O9 HIGH to LOW 5 10 15 5 LOW to HIGH CP0, CP1 O5-9 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR O1 to O9 HIGH to LOW MR O5-9 LOW to HIGH MR O0 LOW to HIGH 10 15 5 10 15 5 10 15 5 10 15 tPLH tPLH tPHL tPLH tPHL tPLH tPHL 140 55 40 125 50 40 145 55 40 125 50 40 115 50 35 110 45 35 130 55 40 280 110 80 250 100 80 290 110 80 250 100 80 230 100 70 220 90 70 260 105 75 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 118 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B MSI
MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA ns ns ns ns ns ns 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15
SYMBOL
60 tTHL 30 20 60 tTLH 30 20
120 60 40 120 60 40
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Hold times CP0 CP1 5 10 15 5 CP1 CP0 Minimum clock pulse width: CP0 = LOW; CP1 = HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 5 10 15 5 10 15 5 10 15 5 10 15 VDD V Dynamic power dissipation per package (P) 5 10 15 fmax tRMR tWMRH tWCPL = tWCPH 80 40 30 50 30 20 60 30 20 6 12 15 40 20 15 25 15 10 30 15 10 12 24 30 ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Figs 4 and 5 10 15 thold thold SYMBOL MIN. 90 40 20 80 40 30 TYP. 45 20 10 40 20 10 MAX. ns ns ns ns ns ns
TYPICAL FORMULA FOR P (W) 500 fi + (foCL) x VDD2 2200 fi + (foCL) x 6000 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B MSI
Fig.4
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0. Hold times are shown as positive values, but may be specified as negative values.
Conditions: CP1 = LOW while CP0 is triggered on a LOW to HIGH transition. tWCP and tRMR also apply when CP0 = HIGH and CP1 is triggered on a HIGH to LOW transition.
Fig.5 Waveforms showing recovery time for MR; minimum CP0 and MR pulse widths.
January 1995
6
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B MSI
Fig.6 Timing diagram.
January 1995
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Philips Semiconductors
Product specification
5-stage Johnson counter
APPLICATION INFORMATION Some examples of applications for the HEF4017B are: * Decade counter with decimal decoding * 1 out of n decoding counter (when cascaded) * Sequential controller * Timer.
HEF4017B MSI
Figure 7 shows a technique for extending the number of decoded output states for the HEF4017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Fig.7 Counter expansion.
Note It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as the this would cause an extra count.
January 1995
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